Computer architectures and related memory systems are well known. Memory systems for server architectures are typically designed to optimize data read and write speed, and usually include error correction and reliability measures in place. System memory, which is implemented as random access memory (RAM), may be realized using dynamic RAM (DRAM) devices, as is well understood. Historically, system memory has included multiple DRAM chips arranged and controlled such that a block of data is distributed across multiple DRAM chips. With such an arrangement, data can be protected in a manner that is similar to that utilized by a redundant array of independent disks (RAID) in a storage context, where independent DRAM channels are used instead of storage disks.
Die-stacked memory architectures have been proposed as an alternative to traditional memory systems that employ distinct DRAM chips arranged in modules, such as dual in-line memory modules (DIMMs). A die-stacked memory utilizes DRAM devices that are physically stacked in a three-dimensional manner. In contrast to a traditional DIMM based memory system that distributes a block of data across multiple DRAM chips, all of the bits for a requested block of data stored in a die-stacked memory architecture may be provided by as few as one die-stacked DRAM device. Consequently, conventional reliability measures that rely on distributed parity bits cannot be utilized in the context of these die-stacked memory arrangements.